00001 /***************************************************************************** 00002 00003 The following code is derived, directly or indirectly, from the SystemC 00004 source code Copyright (c) 1996-2004 by all Contributors. 00005 All Rights reserved. 00006 00007 The contents of this file are subject to the restrictions and limitations 00008 set forth in the SystemC Open Source License Version 2.4 (the "License"); 00009 You may not use this file except in compliance with such restrictions and 00010 limitations. You may obtain instructions on how to receive a copy of the 00011 License at http://www.systemc.org/. Software distributed by Contributors 00012 under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF 00013 ANY KIND, either express or implied. See the License for the specific 00014 language governing rights and limitations under the License. 00015 00016 *****************************************************************************/ 00017 00018 /***************************************************************************** 00019 00020 dcache.h -- Data Cache Unit. 00021 00022 Original Author: Martin Wang, Synopsys, Inc. 00023 00024 *****************************************************************************/ 00025 00026 /***************************************************************************** 00027 00028 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 00029 changes you are making here. 00030 00031 Name, Affiliation, Date: 00032 Description of Modification: 00033 00034 *****************************************************************************/ 00035 00036 00037 struct dcache : sc_module { 00038 sc_in<signed> datain; // input data 00039 sc_in<unsigned> statein; // input state bit MESI(=3210) 00040 sc_in<bool> cs; // chip select 00041 sc_in<bool> we; // write enable 00042 sc_in<unsigned > addr; // address 00043 sc_in<unsigned> dest; // write back to which register 00044 sc_out<unsigned> destout; // write back to which register 00045 sc_out<signed> dataout; // dataram data out 00046 sc_out<bool> out_valid; // output valid 00047 sc_out<unsigned> stateout; // state output 00048 sc_in_clk CLK; 00049 00050 00051 // Parameter 00052 unsigned *dmemory; // data memory 00053 unsigned *dsmemory; // data state memory 00054 unsigned *dtagmemory; // tag memory 00055 int wait_cycles; // cycles # it takes to access dmemory 00056 00057 void init_param(int given_delay_cycles) { 00058 wait_cycles = given_delay_cycles; 00059 } 00060 00061 //Constructor 00062 SC_CTOR(dcache) { 00063 SC_CTHREAD(entry, CLK.pos()); 00064 00065 // initialize instruction dmemory from external file 00066 FILE *fp = fopen("dcache","r"); 00067 int size=0; 00068 int i=0; 00069 int mem_word; 00070 dmemory = new unsigned[4000]; 00071 dsmemory = new unsigned[4000]; 00072 dtagmemory = new unsigned[4000]; 00073 printf("** ALERT ** DCU: initialize Data Cache\n"); 00074 while (fscanf(fp,"%x", &mem_word) != EOF) { 00075 dmemory[size] = mem_word; 00076 dsmemory[size] = 0; 00077 dtagmemory[size] = size; 00078 size++; 00079 } 00080 for (i=size; i<4000; i++) { 00081 dtagmemory[i] = 0xdeadbeef; 00082 dmemory[i] = 0xdeadbeef; 00083 dsmemory[i] = 0; 00084 } 00085 } 00086 00087 // Process functionality in member function below 00088 void entry(); 00089 }; 00090 00091