00001 /***************************************************************************** 00002 00003 The following code is derived, directly or indirectly, from the SystemC 00004 source code Copyright (c) 1996-2004 by all Contributors. 00005 All Rights reserved. 00006 00007 The contents of this file are subject to the restrictions and limitations 00008 set forth in the SystemC Open Source License Version 2.4 (the "License"); 00009 You may not use this file except in compliance with such restrictions and 00010 limitations. You may obtain instructions on how to receive a copy of the 00011 License at http://www.systemc.org/. Software distributed by Contributors 00012 under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF 00013 ANY KIND, either express or implied. See the License for the specific 00014 language governing rights and limitations under the License. 00015 00016 *****************************************************************************/ 00017 00018 /***************************************************************************** 00019 00020 decode.h -- Instruction Decode Unit. 00021 00022 Original Author: Martin Wang, Synopsys, Inc. 00023 00024 *****************************************************************************/ 00025 00026 /***************************************************************************** 00027 00028 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 00029 changes you are making here. 00030 00031 Name, Affiliation, Date: 00032 Description of Modification: 00033 00034 *****************************************************************************/ 00035 00036 00037 struct decode : sc_module { 00038 sc_in<bool> resetin; // input reset 00039 sc_in<unsigned> instruction; // fetched instruction 00040 sc_in<unsigned> pred_instruction; // fetched instruction 00041 sc_in<bool> instruction_valid; // input valid 00042 sc_in<bool> pred_inst_valid; // input valid 00043 sc_in<bool> destreg_write; // register write enable 00044 sc_in<unsigned> destreg_write_src; // which register to write? 00045 sc_in<signed> alu_dataout; // data from ALU 00046 sc_in<signed> dram_dataout; // data from Dcache 00047 sc_in<bool> dram_rd_valid; // Dcache read data valid 00048 sc_in<unsigned> dram_write_src; // Dcache data write to which reg 00049 sc_in<signed> fpu_dout; // data from FPU 00050 sc_in<bool> fpu_valid; // FPU data valid 00051 sc_in<unsigned> fpu_destout; // write to which register 00052 sc_in<bool> clear_branch; // clear outstanding branch 00053 sc_in<bool> display_done; // display to monitor done 00054 sc_in<unsigned > pc; // program counter from IFU 00055 sc_in<bool> pred_on; // branch prediction is on 00056 sc_out<unsigned > br_instruction_address; // branch invoke instruction 00057 sc_out<bool> next_pc; // next pc ++ ? 00058 sc_out<bool> branch_valid; // branch valid signal 00059 sc_out<unsigned > branch_target_address; // branch target address 00060 sc_out<bool> mem_access; // memory access valid 00061 sc_out<unsigned > mem_address; // memory physical address 00062 sc_out<int> alu_op; // ALU/FPU/MMU Opcode 00063 sc_out<bool> mem_write; // memory write enable 00064 sc_out<unsigned> alu_src; // destination register number 00065 sc_out<bool> reg_write; // not implemented 00066 sc_out<signed int> src_A; // operand A 00067 sc_out<signed int> src_B; // operand B 00068 sc_out<bool> forward_A; // data forwarding to operand A 00069 sc_out<bool> forward_B; // data forwarding to operand B 00070 sc_out<bool> stall_fetch; // stall fetch due to branch 00071 sc_out<bool> decode_valid; // decoder output valid 00072 sc_out<bool> float_valid; // enable FPU 00073 sc_out<bool> mmx_valid; // enable MMU 00074 sc_out<bool> pid_valid; // load process ID 00075 sc_out<signed> pid_data; // process ID value 00076 sc_in_clk CLK; 00077 00078 00079 signed int cpu_reg[32]; //CPU register 00080 signed int vcpu_reg[32]; //virtual CPU register 00081 bool cpu_reg_lock[32]; //lock architectural state register 00082 unsigned int pc_reg; //pc register 00083 unsigned int jalpc_reg; //jump back register 00084 00085 //Constructor 00086 SC_CTOR(decode) { 00087 SC_CTHREAD(entry, CLK.pos()); 00088 FILE *fp = fopen("register","r"); 00089 int size=0; 00090 int mem_word; 00091 printf("** ALERT ** ID: initialize Architectural Registers\n"); 00092 while (fscanf(fp,"%x", &mem_word) != EOF) { 00093 cpu_reg[size] = mem_word; 00094 size++; 00095 } 00096 pc_reg = 0; 00097 jalpc_reg = 0; 00098 for (int j =0; j<32; j++) vcpu_reg[j] = 0; 00099 for (int k =0; k<32; k++) cpu_reg_lock[k] = 0; 00100 } 00101 00102 // Process functionality in member function below 00103 void entry(); 00104 }; 00105 00106