00001 /***************************************************************************** 00002 00003 The following code is derived, directly or indirectly, from the SystemC 00004 source code Copyright (c) 1996-2004 by all Contributors. 00005 All Rights reserved. 00006 00007 The contents of this file are subject to the restrictions and limitations 00008 set forth in the SystemC Open Source License Version 2.4 (the "License"); 00009 You may not use this file except in compliance with such restrictions and 00010 limitations. You may obtain instructions on how to receive a copy of the 00011 License at http://www.systemc.org/. Software distributed by Contributors 00012 under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF 00013 ANY KIND, either express or implied. See the License for the specific 00014 language governing rights and limitations under the License. 00015 00016 *****************************************************************************/ 00017 00018 /***************************************************************************** 00019 00020 fetch.h -- Instruction Fetch Unit. 00021 00022 Original Author: Martin Wang, Synopsys, Inc. 00023 00024 *****************************************************************************/ 00025 00026 /***************************************************************************** 00027 00028 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 00029 changes you are making here. 00030 00031 Name, Affiliation, Date: 00032 Description of Modification: 00033 00034 *****************************************************************************/ 00035 00036 00037 struct fetch : sc_module { 00038 sc_in<unsigned > ramdata; // instruction from RAM 00039 sc_in<unsigned > branch_address; // branch target address 00040 sc_in<bool> next_pc; // pc ++ 00041 sc_in<bool> branch_valid; // branch_valid 00042 sc_in<bool> stall_fetch; // STALL_FETCH 00043 sc_in<bool> interrupt; // interrrupt 00044 sc_in<unsigned> int_vectno; // interrupt vector number 00045 sc_in<bool> bios_valid; // BIOS input valid 00046 sc_in<bool> icache_valid; // Icache input valid 00047 sc_in<bool> pred_fetch; // branch prediction fetch 00048 sc_in<unsigned > pred_branch_address; // branch target address 00049 sc_in<bool> pred_branch_valid; // branch prediction fetch 00050 sc_out<bool> ram_cs; // RAM chip select 00051 sc_out<bool> ram_we; // RAM write enable for SMC 00052 sc_out<unsigned > address; // address send to RAM 00053 sc_out<unsigned > smc_instruction; // for self-modifying code 00054 sc_out<unsigned> instruction; // instruction send to ID 00055 sc_out<bool> instruction_valid; // inst valid 00056 sc_out<unsigned > program_counter; // program counter 00057 sc_out<bool> interrupt_ack; // interrupt acknowledge 00058 sc_out<bool> branch_clear; // clear outstanding branch 00059 sc_out<bool> pred_fetch_valid; // branch prediction fetch 00060 sc_out<bool> reset; // reset 00061 sc_in_clk CLK; 00062 00063 // Parameter 00064 int memory_latency; // just a dummy for syntax 00065 00066 void init_param(int given_delay_cycles) { 00067 memory_latency = given_delay_cycles; 00068 } 00069 00070 //Constructor 00071 SC_CTOR(fetch) { 00072 SC_CTHREAD(entry, CLK.pos()); 00073 } 00074 00075 // Process functionality in member function below 00076 void entry(); 00077 }; 00078 00079