00001 /***************************************************************************** 00002 00003 The following code is derived, directly or indirectly, from the SystemC 00004 source code Copyright (c) 1996-2004 by all Contributors. 00005 All Rights reserved. 00006 00007 The contents of this file are subject to the restrictions and limitations 00008 set forth in the SystemC Open Source License Version 2.4 (the "License"); 00009 You may not use this file except in compliance with such restrictions and 00010 limitations. You may obtain instructions on how to receive a copy of the 00011 License at http://www.systemc.org/. Software distributed by Contributors 00012 under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF 00013 ANY KIND, either express or implied. See the License for the specific 00014 language governing rights and limitations under the License. 00015 00016 *****************************************************************************/ 00017 00018 /***************************************************************************** 00019 00020 icache.h -- Instruction Cache Unit. 00021 00022 Original Author: Martin Wang, Synopsys, Inc. 00023 00024 *****************************************************************************/ 00025 00026 /***************************************************************************** 00027 00028 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 00029 changes you are making here. 00030 00031 Name, Affiliation, Date: 00032 Description of Modification: 00033 00034 *****************************************************************************/ 00035 00036 00037 #define BOOT_LENGTH 5 00038 #define MAX_CODE_LENGTH 500 00039 00040 struct icache : sc_module { 00041 sc_in<unsigned > datain; // modified instruction 00042 sc_in<bool> cs; // chip select 00043 sc_in<bool> we; // write enable for SMC 00044 sc_in<unsigned > addr; // address 00045 sc_in<bool> ld_valid; // load valid 00046 sc_in<signed> ld_data; // load data value 00047 sc_out<unsigned > dataout; // ram data out 00048 sc_out<bool> icache_valid; // output valid 00049 sc_out<bool> stall_fetch; // stall fetch if busy 00050 sc_in_clk CLK; 00051 00052 // Parameter 00053 unsigned *icmemory; // icache data memory 00054 unsigned *ictagmemory; // icache tag memory 00055 signed int pid; // process ID 00056 00057 int wait_cycles; // Number of cycles it takes to access imemory 00058 00059 void init_param(int given_delay_cycles) { 00060 wait_cycles = given_delay_cycles; 00061 } 00062 00063 //Constructor 00064 SC_CTOR(icache) { 00065 SC_CTHREAD(entry, CLK.pos()); 00066 00067 // initialize instruction icmemory from external file 00068 pid = 0; 00069 FILE *fp = fopen("icache","r"); 00070 int size=0; 00071 int mem_word; 00072 icmemory = new unsigned[MAX_CODE_LENGTH]; 00073 ictagmemory = new unsigned[MAX_CODE_LENGTH]; 00074 for (size = 0; size < MAX_CODE_LENGTH; size++) { // initialize bad data 00075 icmemory[size] = 0xeeeeeeee; 00076 ictagmemory[size] = 0xeeeeeeee; 00077 } 00078 size = 0; 00079 while (fscanf(fp,"%x", &mem_word) != EOF) { 00080 icmemory[size] = mem_word; 00081 ictagmemory[size] = size; 00082 size++; 00083 } 00084 } 00085 00086 // Process functionality in member function below 00087 void entry(); 00088 }; 00089 00090